1. Field of the Invention
The present invention relates to error checking circuits. More particularly, the present invention relates to an apparatus and method for detecting extraneous start signals which occur within an Instruction Processor (IP) and whose purpose is to start the operation and sequencing controls for a subsection of the processor (e.g. the arithmetic, AR, section of the IP). The present invention in particular can be used in subsections capable of executing overlapping instructions.
2. Description of the Art
Heretofore, complex high speed computing systems have employed numerous checking circuits built into the systems which are directed to automatically correcting bit errors as well as isolating and identifying the logic boards and components which produce these errors to lower the down time and to enable maintenance crews to properly and promptly service the part of the system which produces the errors. Such checking apparatus has included maintenance controllers which log or accumulate information concerning errors that are detected which enable the maintenance personnel to repair the equipment producing the errors.
Instruction Processors (IPs) comprise a critical portion or component of high speed computing systems. IPs are in turn comprised of numerous sections whose timing and response are critically orchestrated by the main control section of the IP. However, some sections of the IP such as the arithmetic section also require additional signals from other sections of the processor as part of the numerous inputs necessary to complete an instruction. After the numerous inputs which are necessary to complete an instruction are assimilated, a start signal is initiated to begin the execution of an instruction. Since the different IP sections embrace numerous logic components, the failure of any logic component can result in raising an erroneous start signal in the arithmetic section of the IP. False or erroneous start signals can initiate the processing of two arithmetic operations in the arithmetic section at the same time which may be manifest in several different ways as follows:
a. The data being processed may become corrupt and create errors which are detected in the arithmetic section registers by through-checking logic such as parity checkers.
b. The data being processed becomes corrupt in the arithmetic section in a manner which does not permit the detection in the arithmetic section registers, thus, produces downstream errors.
c. The erroneous start signals may result in an IP "hang" condition where the false active start condition creates a continuous stuck-at-active-start condition which blocks valid subsequent start signals or a blocking condition may be left active when the controlling sequence designators fail to clear the block due to the false start condition.
In item a above even though the error has been detected in the arithmetic section it creates a troublesome and difficult condition for a repair person or customer engineer because he is prone to believe that the failure is within the arithmetic section where it was detected. This can result in wasted repair time swapping arithmetic PC boards in attempting to fix the problem when the error is not in the arithmetic section.
The arithmetic section is started by one of the arithmetic start signals (AR start) which are input data signals from which the first of a series of sequence designators (SEQ DES) are generated which control all the gating within the arithmetic section. Nearly all further control sequences are contained within the arithmetic section and are based upon the functional coded signals which enable the control logic and select the data path logic. The erroneous selection of data paths and timing control will corrupt the data being processed in the arithmetic section and may or may not generate detectable errors in the arithmetic section. When these outside start signals are in error they usually produce detectable errors in the arithmetic section but most assuredly create some problem down stream from the arithmetic section but not at the components, logic circuits and active gates where the error was instigated.
Accordingly, it would be extremely desirable to provide circuits and a method for detecting extraneous start signals in the arithmetic section to prevent otherwise undetectable data corruption. It is further desirable to provide logic circuits for detecting false starts and data corruption which occurs in the arithmetic section.